In multiprocessor systems, one method for executing stores to a shared cache involves using a pipeline to perform a directory lookup in order to determine which compartment the data is to be store to and then to send this information to the cache. Once this compartment information is obtained it is possible for subsequent stores to the same line to avoid using the pipeline by using address compares and a dedicated pipeline that stores directly to the cache, thus avoiding the directory lookup and freeing up system resources.
When the cache being stored to is interleaved, additional logic is needed to model the behavior of the cache based on previous operations. The model is used to determine whether or not an operation should make a request and to avoid potential interleave conflicts.
Given an arrangement of using a cache interleave model along with both shared and dedicated store resources, additional logic to arbitrate between requests from multiple chips must be implemented. When the store logic has requests active for both pipelines, it is first necessary to ensure that any interleave conflicts will be avoided before granting either request. It is also important to make efficient use of the interleaves by allowing both pipelines to have access whenever possible. Because of this, simpler schemes may not suffice. Both pipelines should be granted access whenever possible and all conflicts should be avoided.
Unfortunately, the above systems may not effectively and efficiently meet the storage needs of a computer system.